Tone generating system

ABSTRACT

A system for generating sustained pulse trains having frequencies related to the fundamental frequency of a controlling input signal includes means for extracting the fundamental frequency of the input, a first register for accumulating a count related to this fundamental frequency, a second register for repeatedly producing an output at selectable rates which are related to the accumulated count and divider circuits for producing various ratios of the output. The accumulated count can be adjusted to compensate for deviations of the input frequency from a desired scale.

Staes [451 Nov. 26, 1974 TONE GENERATING SYSTEM [76] Inventor: Leroy Daniel Young, Jr., 8801 Fontainebleau Blvd., Apt. 308, Miami, Fla. 33126 Primary Examiner-John Zazworsky [57] ABSTRACT [22] Flled: 1973 A system for generating sustained pulse trains having [21] App], No; 329,534 frequencies related to the fundamental frequency of a controlling input signal includes means for extracting the fundamental frequency of the input, a first register [52] Cl 328/140 307/271 328/63 for accumulating a count related to this fundamental 328/130 frequency, a second register for repeatedly producing [5]] lift. Cl. 03b 3/08 an output at Selectable rates which are related to the [58] Fleld of Search 307/271 accumulated count and divider circuits for producing 328/130 15-18 324/78 79 various ratios of the output. The accumulated count can be adjusted to compensate for deviations of the [56] References C'ted input frequency from a desired scale. UNITED STATES PATENTS 3,568,069 3/1971 Gabor 328/48 x 40 Clams 5 D'awmg F'gures 3o 34 i NEW 0 TRDIIK b a 5 PAL yfifl 6 9a rs wasta e ra 32 96 1 2 AMPLIFIER EXTRACTOR 2O CLEAR GEN COUNT DOWN ZERO ENABLE l lcLEAR REG'STER DE PE Ci TBR |oo NOT CLEAR AND NOT ENABLE I08,

66 I02 l atlas stats SUBTRACT OUTPUTS PULSE SHAPING PATENTEL wa 4 3.851.265

no "(couNT I64) (COUNT 232) FIG. 4

ALLOWABLE COUNTS FOR TEMPERED SCALE DECIMAL I NA R1 232 IIIOIOOO I95 IIQOOOII I84 |o|||o0o I74 so: |||o l64 IOIOOIOO I55 |oo||0|| 14s |0o|oo|o I38 IOOOIOIO I30 |ooooo|o I23 o1|||o|| TONE GENERATING SYSTEM BACKGROUND OF THE INVENTION 1. Field of the Invention This invention relates to musical instruments and more particularly to a system for generating and sustaining different frequency outputs related to an imput musical waveform such as that produced by a known musical instrument.

2. Description of the Prior Art Many tone or soound generating systems have been developed for use with musical instruments such as electric guitars to provide the musician with a variety of voicings or outputs electronically derived from the output of the musical instrument being played. However most of these presently known systems have vari ous limitations. Some of the known systems require extensive modification of the musical instrument to be utilized so that special pickups and like apparatus can be provided thereon. Others of the presently known systems essentially comprise systems for merely revoicing the sound produced on the instrument itself.

Accordingly, it is an object of this invention to provide a system external to the musical instrument being utilized for sampling the waveform produced thereby and generating sustained constant amplitude outputs related to the fundamental frequency of this waveform by integer and non-integer ratios.

It would be very beneficial in many cases to be able to produce and sustain an output which is related to the fundamental frequency produced by a musical instrument. For example, it would be advantageous to produce and sustain an output having a frequency related to the fundamental frequency of the plucked output of an electric guitar. Such a sustained or repeatedly voiced output could continue from one plucked output of the guitar to the next regardless of pause duration. Existing musical voicing systems do not offer such a feature.

Accordingly, it is another object of this invention to provide a system for producing and sustaining a frequency output related to the output of musical instrument being played.

Still another object of this invention is to provide a system for producing outputs related to inputs from a musical instrument or voice but which are compensateed for deviations of the inputs from a preselected scale.

SUMMARY OF THE INVENTION The foregoing objects and others are achieved in accordance with the invention by a system which includes circuit means for extracting the fundamental frequency of an input from a musical instrument. A generator responsive to the. extracting circuit produces control pulses which gate clock pulses into a first register to accumulate a count therein related to the fundamental frequency. This count can be rounded off to compensate for deviations of the fundamental frequency from a preselected scale. The accumulated count is subsequently gated into a storage register. The count in the storage register is transferred in a repetitive sequence to a third register which produces output pulses at a rate related to that at which the count is accumulated in the first register and hence related to the fundamental frequency of the original input. Thus the third regisdesired ratios. The frequency of the output from the third register can be higher or lower than the inputted fundamental frequency.

BRIEF DESCRIPTION OF THE DRAWING FIG. 1 is a block diagram representation of the system of this invention;

FIG. 2A-D is a representation of a complexwaveform input to the system of FIG. 1 and the signals in portions of the system at various time intervals of the input;

FIG. 3 is a more detailed representation of the fundamental frequency extractor portion of FIG. 1;

FIG. 4 is a tabular representation of a tempered scale to which the outputs of the system of FIG. 1 are to be related; and

FIG. 5 is a more detailed representation of a portion of the system for obtaining the scale of FIG. 4.

DETAILED DESCRIPTION Referring now to FIG. I which shows a block diagram of the system 101 of this invention, a complex musical waveform which can comprise the output of an electric guitar, microphone, or other instrument is transferred to system 101 over input lead 2 and inputted to buffer and amplifier 4. Buffer and amplifier 4 advantageously include a unity gain buffer stage to isolate the input and to adjust buffer and amplifier 4 to the particular type of input being used. Buffer and amplifier 4 also includes an amplifying stage for raising the level of the signal to the remainder of system 101. A gain of approximately fifty in the amplifying stage is normally desirable. Buffer and amplifier 4 can comprise operational amplifiers known in the art such as the uA709 operational amplifier commercially available from Signetics Corporation.

The complex waveform having the proper level is fed over lead 5 from buffer and amplifier 4 to fundamental frequency extractor 6 which extracts or determines the fundamental frequency thereof and outputs a square wave having this-fundamental frequency. As shown in FIG. 2A the complex waveform 8 may cross a reference level 10 such as zero volts a number of times durwaveform. Thus each time waveform 8 passes through threshold level 12 as shown in FIG. 2A a normal threshold detector changes states as shown in FIG. 2C.

However by combining a zero crossing detector 7 with a threshold detector 9 in a special way as shown in FIG. 3, a fundamental frequency extractor 6 can be obtained which is substantially insensitive to amplitude, frequency and waveform complexity. The complex waveform 8 on lead 15 is fed to both a zero crossing detector 7 and a threshold detector 9 which produce outputs on leads 16 and 18, respectively, as previously discussed and shown in FIG. 2B and 2C, respectively. The outputs from zero crossing detector 7 and threshold detector 9 are fed to respective sides or gates 13 and 14 of a flip-flop 11. Flip-flop 11 is toggled only once per cycle of waveform 8 and produces an output lead 20 a varying duty cycle square wave having a period equal to the fundamental period of waveform 8 as shown in FIG. 2D. Zero crossing detector 7 and threshold detector 9 can comprise well known devices such as the uA7 l integrated comparators commercially available from Signetics Corporation. Flip-flop 11 can also comprise a known device such as two gates from a 7,400 series integrated circuit package commercially available from Motorola, Inc.

System 101 can operate in two modes which are termed a hold mode and a track mode. In the hold mode, which advantageously is utilized with short term input waveforms such as plucked notes from a guitar, system 101 acts as a frequency saver by generating and sustaining an output having a frequency which is related to the frequency of the input until a new input is received regardless of the time interval between inputs. In the track mode, which is advantageously utilized with a substantially continuous input waveform, system 101 produces outputs which are related to and follow or track the input in real time. The particular mode desired is determined by the position of switch 22. Additionally, in each mode, the outputs of system 101 can be adjusted if desired to compensate for deviations of the input from a desired freqeuncy scale, i.e., to compensate for sharp" or flat" inputs or to produce discrete frequency outputs from a gliding input such as a voice input. These various waves of operation will now be discussed in detail with reference first to the hold mode with an unadjusted or uncompensated output. In this first discussed arrangement, switches 60a and 6012, which advantageously are tied together for synchronized operation, are closed on the b and 0 terminals thereof, respectively.

In the hold mode as determined by switch 22, the fundamental frequency square wave on lead 20 is transmitted to a new note detector 26 and an enable and clear generator 28. Each time a new signal is received from lead 20, e.g., each time a new plucked input is received on lead 2, detector 26 produces a pulse which is transmitted to generator 28 through leads 30, terminal a of switch 22 and lead 32. New note detector 26 advantageously comprises two series connected retriggerable monostable multivibrators such as those ob tainable commercially as 74123 monostable multivibrators from Signetics Corporation having adjustable R-C timing circuits associated therewith. Upon receipt of an initial input, the first multivibrator fires or sets and causes the second multivibrator to produce the narrow pulse which is transmitted to generator 28. The first multivibrator will remain set because of its associated timing circuit until the subsequent occurrence of a pause between inputs having a duration greater than the preselected period of the timing circuit. For example, the period of the timing circuit associated with the first mulltivibrator advantageously can be preselected to equal l milliseconds. Accordingly, inputs separated by less than milliseconds will simply retrigger the first multivibrator causing it to remain set so that no additional trigger pulses are outputted by detector 26.

This prevents the detector 26 from responding to different cycles of the same input or to very fast inputs while the system is in the hold mode. When the first multivibrator senses a pause of greater than 15 milliseconds, the associated timing circuit times out causing the multivibrator to reset and again be conditioned for generating a trigger pulse when a new input is received.

The pulse on lead 32 triggers generator 28 and causes it to output enable and clear pulses on leads 36 and 40, respectively, with the enable pulse having width equal to the period of the fundamental frequency signal on lead 20. Generator 28 can comprise what is known in the prior art as a single-pulse generator such as that shown in 400 Ideas for Design, Hayden Book Co., 1971, page 194 (a collection of circuits for Electronic Design). Such a generator is essentially a two-bit or two-stage binary counter comprising a J-K flip-flop which is cleared by the leading edge of each trigger pulse on lead 32 and is toggled by negative transitions of the signal on lead 20 from extractor 6. The setting of the second stage of such a flip-flop locks up or inhibits the first stage thereof to prevent further toggling until the flip-flop is again cleared. Thus when initiated by a trigger pulse on lead 32, generator 28 emits a single enable pulse from the output of stage 1 thereof onto lead 36 which is equal in width to the presently received pulse on lead 20, i.e., to the fundamental period of the input signal. Generator 28 is thereafter idle until another trigger pulse is received. Generator 28 also can include a known one-shot multivibrator such as the previously mentioned Signetics Corporation N74l23 multivibrator which responds to the leading edge of the trigger input on lead 32 to produce the clear pulse on lead 40. Generator 28 can further include a standard two-input gate which responds to the absence of the clear and enable pulses to generate the not clear and not enable" pulse on lead 38. The clear signal on lead 40 is transmitted to a count up register 84 which is initialized and prepared for counting thereby. The enable pulse on lead 36 is transmitted to OR gate 44 which has the other input 45 thereof grounded through terminal b of switch 60a. Accordingly, gate 44 produces an output pulse having the fundamental period which is transmitted over lead 48 to enable a divider 50. Divider 50 advantageously can be a divide by eight circuit which can comprise a known device such as a 7493 binary counter commercially available from Signetics Corporation. Divider 50 receives clock pulses from an oscillator 52 over lead 54, divides the frequency of these pulses, and transmits outputs to count up register 84 through lead 56, the 0 terminal of switch b, and lead 62. The clock pulses from oscillator 52 are also transmitted directly to a count down register 68 over lead 54 without any modification such as frequency division. Oscillator 52 can comprise a Schmitt trigger such as the N74l3 device manufactured by Signetics Corporation which produces pulses at a rate of approximately 200 KHz for advantageous use with an eight-bit register.

The pulses from divider 50 are gated into count up register 84 for the duration of the enable pulse on lead 36. Accordingly, the accumulated count in register 84 is directly related to the fundamental frequency of the input signal on lead 2.

Utilizing the pulses from oscillator 52, count down register 68 repeatedly transfers the count stored in a holding register 76, counts down to zero, or some other initial count, transfers again from holding register 76, etc. A zero count detector 98 detects when count down register 68 reaches zero, or some other initial count, and then enables gate 72 over lead 106 to again transfer the stored count from holding register 76 to count down register 68 over leads 70 and 74. Zero count detector 98 also provides an input to gate 80 over lead 108 when a count is not being transferred from register 76 to register 68, i.e., when gate 72 is not enabled. Detector 98 can comprise an edge-triggered one-shot multivibrator having Q and 6 outputs, such as the previously mentioned Signetics Corporation N74123 multivibrator, which is controlled by the most significant bit of count down register 68. When register 68 reaches zero, or some other initial count, the most significant bit recycles or changes to a one" state which can trigger the multivibrator to emit a narrow pulse from its Q output on leads 106 and 100. Lead 108 is connected to the 6 output of the multivibrator.

When the enable pulse terminates on lead 36, generator 28 produces another pulse which can be labeled a not enable and not clear pulse which is transmitted to AND gate 64 over lead 38. This pulse together with the output from gate 44 via lead 46, inverter 47 and lead 49 causes gate 64 to transmit an output on lead 66 to gate 80 whenever register 84 is not being cleared or counted into. Accordingly, the accumulated count in count up register 84, which is related to the fundamental frequency of the input waveform, is transmitted to holding register 76 whenever gate 80 is enabled by inputs on both leads 66 and 108. This accumulated count is subsequently repeatedly transferred to count down register 68 as previously discussed.

The counting rate of count down register 68 as compared with the counting rate of count up register 84 equals the divisor of divider 50, i.e., equals eight in the illustrative embodiment. Thus in the illustrative embodiment register 68 produces a zero count at a frequency eight times greater than the fundamental frequency of the input to system 101. This zero count is detected by detector 98 which also produces output signals or pulses on lead 100 at eight times this fundamental frequency. The pulses on lead 100 are transmitted to division circuits 102 which can produce outputs or pulse trains 104 having frequencies related to the fundamental frequency by any desired integer and noninterger ratios. For example, commonly desired ratios are 4,2, /2, l and 4/3 which respectively represent two octaves above, one octave above, one octave below, two octaves below, and a musical fifth of the fundamental frequency.

The outputs 104 from division circuits 102 can be fed to pulse shaping circuits 105 and amplifying circuits 107 which are well known in the art to obtain a variety of voicings 109 of the input waveform.

It should be apparent that a count transferred to holding register 76 will remain therein until it is replaced by an updated count from count up register 84 regardless of the interval of time between such updating. Count down register 68 will-continue to cycle the count stored in register 76 and produce outputs as long as oscillator 52 provides pulses thereto. Thus outputs 104 having frequencies related to the fundamental frequency of an input by any desired ratio can be generated and sustained or repeated indefinitely by thissystern.

As previously mentioned it may be desirable in some applications to have the outputs 104 of system 101 as produced by a sequence of inputs to be related to each other in a specified manner such as notes on a desired scale regardless of whether the inputs themselves are precisely so related. This requires that only specified counts which lie on this desired scale be allowed to accumulate in count up register 84. This requires that counts related to off-scale inputs be rounded off to one of the allowed counts, i.e., one of the counts related to a note on the scale. It would be desirable if this rounding off always could be to the nearest allowable count so that both flat and sharp inputs could be compensated. Requiring that the actual count always be rounded to the closest allowable count, i.e., exact rounding off, increases the complexity of the system. However an approximate rounding off as will now be described can provide substantially the same benefits as the exact rounding off without the resulting complexity.

FIG. 4 lists in a tubular format, in both decimal and binary form, twelve allowable accumulated counts in register 84 which would comprise one octave of the tempered music or frequency scale within an accuracy of 0.15 percent. Such a range advantageously can be utilized where register 84 comprises an eight bit register. Twelve decoders 88 to decode the twelve allowable counts are connected to register 84. For example, each decoder 88 can comprise a single eight-input AND gate 110 having the eight inputs 86 thereof connected to the appropriate bits B1-B8, or B 1-B8, of register 84 as shown in FIG. 5. When register 84 accumulates a count equal to that coded in one of the decoders 88, that particular decoder 88 produces a pulse which is transmitted to OR gate 92 on lead 90. For example, when register 84 accumulates a decimal count of 232, i.e., a binary count of lllOlOOO, as represented by B8 B7 B6 B8 B4 F3 B 2 B l, where the bar indicates a zero," the decoder 88 having this count coded therein will produce an output pulse. Gate 92 produces an output signal whenever any one of decoders 88 provides a pulse thereto which is transmitted to a flip-flop 42 via lead 94.

In this configuration of system 101, switches 60a and 601; are moved from the previously discussed position so that terminals a and d are respectively contacted. Thus the clock pulse from divider 50 which are being transmitted into register 84 to accumulate the appropriate count therein related to the fundamental frequency of the input are now routed through a subtractor 58. Subtractor 58 determines the break point between two allowable counts in the desired scale at which the rounding off in register 84 changes from the next lower allowable count to the next higher allowable count. An inspection of the scale in FIG. 4 indicates that on the average there is approximately a difference of eight between the allowable counts in the lower portion of the scale. Accordingly, setting the break point at four above any allowable count puts this break point at approximately the midpoint between two adjacent allowable counts which is very desirable because it is very close to exact rounding off.

Subtractor 58 can comprise a simple circuit for counting a specified number of clock pulses from divider 50 before allowing the transmission of any clock pulses-to count up register 84. For example, in the illustrative embodiment, Subtractor 58 can comprise a flipflop and an AND gate. The flip-flop could be cleared by each clear pulse or signal from generator 28 on lead 59. The flip-flop could then be set by the first four clock pulses from divider 50 to enable the AND gate and permit transmission of all subsequent clock pulses to register 84 through terminal d of switch 60b. Thus the count initially accumulated in register 84 is four less than the actual count required to exactly relate to the input signal. If this initial count in register 84 does not equal one of the allowable counts, the initial count is always rounded to the next higher allowable count. Thus the final accumulated count in register 84 is exactly the same as if rounding off in both directions were performed with the break point for rounding off being four above the next lower allowable count, i.e., approximately midway between the adjacent allowable counts. For example, suppose that an input signal on lead 2 has a fundamental frequency corresponding to a count of 133 in register 84. After the subtraction of the first four pulses by subtractor 58, the initial count accumulated in register 84 would be 129. This does not correspond with any allowable count of the scale shown in FIG. 4. Thus this initial count would be rounded off to 130, the next higher allowable count and which is also the closest allowable count to the actual count of 133 in this case. Correspondingly, an input signal having a related count of 134 or 135 would be rounded to 130 or 138, respectively. This approximate rounding off provides substantially the same benefits of compensation for flat or sharp inputs as rounding off from a precise midpoint with substantially less complexity.

The rounding off is accomplished by requiring register 84 to continue counting after termination of the enable signal on lead 36 until an allowable count is reached unless the enable signal is terminated when the register 84 contains such an alllowable count. The outputs from gate 92 on lead 94 in conjunction with the enable pulse on lead 36 toggles flip-flop 42 at appropriate intervals so that flip-flop 42 provides an alternate enabling signal to gate 44 through terminal a of switch 60a if the enable pulse on lead 36 is terminated when register 84 contains a count which requires rounding, i.e., does not contain an allowable count. Thus gate 44 continues to gate pulses from oscillator 52 into register 84 until the next allowable count is reached at which time an output from gate 92 caused by an output from a decoder 88 switches flip-flop 42 to a state which removes the enabling signal from gate 44. Simultaneously, the output from gate 44 is transmitted to gate 64 over lead 46, inverter 47 and lead 49 to cause gate 64 to inhibit transfer from count up register 84 to holding register 76 until the final allowable count has been accumulated in register 84, i.e., until the counting into register 84 has been terminated by the disabling of gate 44.

The foregoing detailed discussion has dealt primarily with operation of system 101 in the hold mode of operation which advantageously is utilized with short term inputs such as the plucked notes of a guitar. However the system can be made to output frequency multiples which track a continuous, frequency-varying input. In the track mode the b terminal of switch 22 is operated so that divider 24 replaces new note detector 26 in the operating path. There is normally no necessity for the outputs 104 to track a continuous input on a cycle-bycycle basis. Normally a more limited sampling ofa continuous input such as every fourth cycle will provide acceptable tracking of the input. Divider 24 determines the sampling rate and in the illustrative embodiment is a divide-by-four circuit. Thus divider 24 produces an output on every fourth cycle of the input signal on lead 2 which is transmitted via lead 34, terminal b of switch 22 and lead 32 to generator 28 which is caused to generate the clear and enable pulses previously discussed on every fourth cycle of the input signal. The subsequent operation of the remainder of system 101 in the track mode is the same as previously discussed with reference to the hold mode.

In the track mode the updating of count up register 84 on every fourth cycle of the continuous input is normally sufficient to produce good tracking of the input signal by outputs 104.

As previously illustrated by specific examples, system 101 can be readily implemented by utilizing circuit apparatus known in the art. Advantageously much of this apparatus can comprise integrated circuit packages as further shown by the following examples. Divider 24 and similar portions of division circuits 102 can comprise J-K flip-flops such as those available commercially as part number MC3062 from Motorola, Inc. Count up register 84 as well as portions of division circuits 102 can comprise four-bit binary counters such as the 7493 binary counter previously mentioned with respect to divider 50. Registers 76 and 68 can also comprise commercially available binary counters such as the 7475 and 7416 binary counters, respectively, made by Signetics Corporation. Flip-flop 42 and the numerous gates can comprise portions of integrated circuit packages. This listing of commercially available apparatus for implementing system 101 is merely for purposes of showing the practical advantages of applicants invention. It is in no way to be interpreted as a restriction of his invention to such listed apparatus. Numerous other ways of implementing various portions of the system will be readily apparent to those skilled in the art.

Various modifications to the described embodiment of system 101 can be made. For example, oscillator 52 could' be replaced by two oscillators one of which drives register 84 and the other of which drives register 68. In such a case divider 50 would not be required in order to have registers 68 and 84 count at different rates. Rather the ratio of the counting speeds of the two registers, and accordingly the ratio of the frequency of the output on lead to the fundamental frequency of the input signal, would equal the ratio of the frequencies of the two oscillators. The frequency of oscillator 52 and the divisor of dividers 24 and and 50 can readily be changed. Registers 68, 76 and 84 can be modified to count in directions different from those discussed and to be more than eight stages in length for desired accuracy. It is to be understood that such modifications are skill-of-the-art contributions falling within the spirit and scope of this invention.

What is claimed is:

l. A system for repeatedly generating and sustaining output signals having frequencies related to the fundamental frequency of a controlling input signal having a complex waveform and a varying amplitude level comprising, in combination:

first means including a fundamental frequency extractor for determining said fundamental frequency of said input signal and producing a square wave output having said fundamental frequency;

second means responsive to said first means for storing a signal related to said fundamental frequency; and

output means responsive to said second means for producing in a repetitive e sequence output signals having frequencies determined by said signal stored in said second means whereby said output signals have frequencies related to said fundamental frequency of said input signal.

2. The system of claim 1 wherein said extractor includes:

a level crossing detector for producing an output when said level of said waveform passes through a first reference level;

a threshold detector for producing an output when ssaid level of said waveform exceeds a second reference level; and flip-flop having a first side connected to said level crossing detector and a second side connected to said threshold detector, said second side having an output terminal, whereby said square wave is produced at said output terminal of said flip-flop.

3. The system of claim 1 wherein said second means includes:

a first register adapted for accumulating a pulse count therein; and

a frequency source responsive to said first means for producing pulses to said first register for a period of time related to said fundamental frequency of said input signal whereby said count accumulated in said register is a measure of said frequency.

4. The system of claim 3 wherein said second means further includes:

a generator responsive to said first means for producing first and second control pulses at a rate determined by said fundamental frequency, said first control pulse having a duration proportional to the period of said input signal;

means for connecting said second control pulse to said first register for initializing said count therein; and

gatingmeans responsive to said first control signal for gating said pulses to said first register for said duration.

5. The system of claim 4'wherein said input signal comprises a plurality of discrete segments separated by time intervals, said first means determines said fundamental frequency of each of said segments, and said second means further includes;

a detector responsive to said first means for detecting said fundamental frequency of each of said segments and generating a trigger output in response thereto; and

means for connecting said trigger output to said generator for causing said generator to produce one of each of said first and second control pulses for each of said segments, whereby said count accumulated in said first register at a particular time is related to said fundamental frequency of one of said segments comprising said input at said particular time.

6. The system of claim 4 wherein said input signal lid each cycle of said wave, and said second means includes:

a divider responsive to said first means for generating a trigger output for every n'" cycle of said wave; and

means for connecting said trigger output to said generator for causing said generator to produce one of each of said first and second control pulses at ever n one of said cycles, said duration of said first control pulse being proportional to the period of said n" cycle, so that said count accumulated in said first register is updated every n' cycle and thereby tracks the frequency of said wave, where n is any positive integer.

7. The system of claim 6 wherein n equals four.

8. The system of claim 3 wherein said output means includes:

a second register having an initial count therein;

means for changing said initial count by an amount equal to said accumulated count in said first register in a repetitive sequence;

means for cycling said second register at a rate proportional to the frequency of said frequency source to cause returns of said second register to said initial count; and

means for detecting said returns to said initial count and producing an output signal in response thereto whereby said output signal is repeatedly produced and has a frequency related to said fundamental frequency of said input signal.

9. The system of claim 8 wherein said initial count equals zero, said accumulated count is added to said second register and said cycling means causes said second register to count down from said accumulated count to zero.

10. The system of claim 8 wherein said changing means includes:

a third register for receiving and storing said accumulated count from said first register;

a first gate responsive to said detecting means for transferring said accumulated count from said third register to said second register upon each of said returns to said initial count; and

a second gate responsive to said detecting means fortransferring said accumulated count from said first register to said third register whenever a new one of said counts is accumulated in said first register whereby said third register always contains a count related to said fundamental frequency of said input signal.

11. The system of claim 8 including:

a divider between said frequency source and said first register for dividing the frequency of said pulses from said frequency source by a factor of m, where m is any positive integer; and

said cycling means includes means for connecting,

mental frequency of said input signal by any desired ratio can be obtained.

14. The system of claim 13 further including pulse shaping circuits for shaping said plurality of outputs and means for amplifying said outputs whereby a variety of voicings having frequencies related to said frequency of said input signal can be obtained.

15. The system of claim 3 including:

a plurality of decoders each of which is responsive to the accumulation ofa respective allowable count in said first register; and

means responsive to said decoders in the absence of one of said respective counts for extending said period of time during which said pulses are provided to said first register until one of said respective allowable counts is accumulated in said first register, whereby said accumulated count is srestricted to one of said respective allowable counts.

16. The system of claim 15 including a subtractor between said frequency source and said first register for subtracting the first x of said pulses provided to said first register, where x is any positive integer, whereby said count accumulated in said first register is rounded off to one of the two closest ones of said respective counts.

17. The system of claim 16 wherein x approximately equals one-half the average difference between said respective allowable counts whereby said count accumulated in said first register is normally rounded off to the nearer one of said two closest ones of said respective counts.

18. The system of claim 16 wherein x equals 4.

19. The system of claim 1 including buffer and amplifier circuits for isolating and amplifying said input signal, respectively, applied to said first means.

20. The system of claim 19 wherein said buffer circuit provides a gain of approximately one and said amplifying circuit provides a gain of approximately 50.

21. The system of claim 1 wherein said output means comprises;

a counting means having an initial count therein;

means for changing said initial count by an amount proportional to said signal stored in said second means in a repetitive sequence;

means for repeatedly cycling said counting means at a preselected rate to cause returns thereof to said initial count; and

means for detecting said returns to said initial count and producing output signals in response thereto, said output signals having frequencies related to said fundamental frequency of said input signal.

22. The system of claim 21 wherein said changing means includes:

a storing means responsive to said signal in said second means for accumulating a count therein proportional to said signal;

first gating means responsive to said detecting means for transferring said count in said storing means to said counting means each time said counting means returns to said initial count; and

means responsive to the storing of a new one of said signals in said second means for updating said count accumulated in said storing means.

23. The system of claim 22 further including division circuits for dividing said frequencies of said outputs by a plurality of preselected numbers so that a plurality of outputs having frequencies related to said fundamental frequency of said input signal by any desired ratios can be obtained.

24. The system of claim 23 further including pulse shaping circuits for shaping said plurality of outputs and amplifying means for amplifying said plurality of outputs whereby a variety of voicings having frequencies related to said fundamental frequency of said input signal can be obtained.

25. The system of claim 1 wherein said;

second means includes a first register for accumulating a pulse count therein, and a frequency source responsive to said frequency extractor for providing pulses to said first register for a period of time proportional to said fundamental frequency so that said count accumulated by said first register is proportional to said fundamental frequency; and

said output means includes a second register having an initial count therein, means for changing said initial count by an amount equal to said accumulated count in said first register in a repetitive sequence, means for repetitively cycling said second register at a rate proportional to the frequency of said frequency source to cause returns thereof to said initial count, means for detecting said returns and producing output signals in response thereto, said output signals having frequencies related to said fundamental frequency and being produced in a repetitive sequence.

26. The system of claim 25 wherein said second means further includes a generator responsive to said extractor for generating first and second control pulses, said second control pulse being utilized to initialize said first register, said first control pulse having a duration equal to said fundamental frequency, and a gate responsive to said first control pulse to transfer said pulses to said first register.

27. The system of claim 26 including a divider for dividing the frequency of said pulses transferred to said first register by a factor of m and wherein said cycling means includes means connecting said pulses to said second register to cause said second register to count at a rate m times said first register, whereby said detecting means produces an output signal having a frequency m times said fundamental frequency where m is any positive integer.

28. The system of claim 27 wherein said changing means includes a third register for receiving and storing said accumulated count, a first gate responsive to said detecting means for transferring said accumulated count from said third register to said second register upon each of said returns of said second register to said initial count; and a second gate responsive to said detecting means and said generator means for transferring said accumulated count from said first register to said third register after the termination of each of said control pulses and during a time when said first gate is inactive.

29. The system of claim 28 including division circuits for dividing the frequency of said output signal by a plurality of factors so that outputs having frequencies related to said fundamental frequency by any desired ratios can be obtained.

30. The system of claim 29 wherein said plurality of factors includes the integers l, 2, 4, 6, 8, l6, and 32.

31. The system of claim 30 including:

a plurality of decoders each of which is responsive to the accumulation of a respective allowable count in saidfirst register; and

means responsive to said decoders in the absence of one of said respective allowable counts for extending said period of time during which said pulses are provided to said first register until one of said respective counts is accumulated in said first register, whereby said accumulated count is restricted to one of said respective allowable counts.

32. The system of claim 31 including a subtractor for subtracting the first x of said pulses transmitted by said divider towards said first register where x is any positive integer, whereby said count accumulated in said first register is rounded off to one of the two closest ones of said respectiveallowable counts.

33. The system of claim 32 including means for isolating and amplifying said input signal presented to said frequency extractor.

34. The system of claim 33 wherein said input signal comprises a continuous waveform, and including meansresponsive to said frequency extractor for causing said generator to produce one of each of said first and second control pulses on every n'" cycle of said continuous waveform where n is any positive integer, whereby said output signal tracks said fundamental frequency of said waveform.

35. The system of claim 25 including a second frequency source connected to said second register to cause said second register to count at a rate of m times said first register, where m is the ratio of the frequency of said second frequency source to the frequency of said frequency source, whereby said output signal produced by said detector has a frequency m times said fundamental frequency.

36. Apparatus for generating an output signal having a frequency which is proportional to the fundamental frequency of an input signal having a frequency'varying waveform comprising, in combination:

a frequency extractor for extracting said fundamental frequency for each cycle of said waveform;

a division circuit responsive to said extractor for producing a trigger pulse on every n" cycle of said waveform, where n is any integer;

a first counting register adapted for accumulating a pulse count therein;

a frequency source for providing pulses to said first register;

a generator responsive to said trigger pulse for generating a second control signal for initializing said first register and a first control signal having a duration proportional to said fundamental frequency of said n"' cycle;

a gate responsive to said first control signal for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency of said n" cycle;

a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control signals, whereby said accumulated count is updated every n"! cycle;

a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output at a frequency proportional to said accumulated count; and

means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count to said second register, whereby said output signal has a frequency which tracks said fundamental frequency of said .waveform.

37. The system of claim 15 wherein said plurality of decoders comprises twelve decoders and said respective allowable counts have specified ratios with respect to each other.

38. The system of claim 33 wherein said input signal comprises a plurality of discrete segments separated by time intervals and including means responsive to said frequency extractor for causing said generator to produce one of each of said first and second control pulses for each of said discrete segments, whereby the frequency of said output signal is proportional to said fundamental frequency of said discrete segments.

39. Apparatus for generating an output signal having a frequency proportional to the fundamental frequency ofa discrete segment of an input signal including a plurality of discrete segments separated by time intervals, and sustaining said output signal until a subsequent one of said discrete segments is received by said apparatus comprising, in combination;

a frequency extractor for extracting said fundamental frequency of said discrete segment;

a first counting register adapted for accumulating a pulse count therein;

a frequency source for providing pulses to said first register;

a generator responsive to said frequency extractor upon the receipt of each of said discrete segments for generating a second control pulse for initializing said first register and a first control pulse having a duration proportional to said fundamental frequency;

a first gate responsive to said first control pulse for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency;

a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control pulses, whereby said accumulated count in said storage register is updated for each of said discrete segments;

a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output having a frequency proportional to said accumulated count and thereby to said fundamental frequency; and

means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count from said storage register to said second register, whereby said output signal associated with a particular one of said discrete segments is repeatedly produced until a subsequent one of said discrete sergments is received.

40. Apparatus in accordance with claim 39 including division circuits for dividing the frequency of said output signal by a plurality of factors, whereby signals having frequencies related to said fundamental frequency by any desired ratios can be obtained. 

1. A system for repeatedly generating and sustaining output signals having frequencies related to the fundamental frequency of a controlling input signal having a complex waveform and a varying amplitude level comprising, in combination: first means including a fundamental frequency extractor for determining said fundamental frequency of said input signal and producing a square wave output having said fundamental frequency; second means responsive to said first means for storing a signal related to said fundamental frequency; and output means responsive to said second means for producing in a repetitive e sequence output signals having frequencies determined by said signal stored in said second means whereby said output signals have frequencies related to said fundamental frequency of said input signal.
 2. The system of claim 1 wherein said extractor includes: a level crossing detector for producing an output when said level of said waveform passes through a first reference level; a threshold detector for producing an output when ssaid level of said waveform exceeds a second reference level; and a flip-flop having a first side connected to said level crossing detector and a second side connected to said threshold detector, said second side having an output terminal, whereby said square wave is produced at said output terminal of said flip-flop.
 3. The system of claim 1 wherein said second means includes: a first register adapted for accumulating a pulse count therein; and a frequency source responsive to said first means for producing pulses to said first register for a period of time related to said fundamental frequency of said input signal whereby said count accumulated in said register is a measure of said frequency.
 4. The system of claim 3 wherein said second means further includes: a generator responsive to said first means for producing first and second control pulses at a rate determined by said fundamental frequency, said first control pulse having a duration proportional to the period of said input signal; means for connecting said second control pulse to said first register for initializing said count therein; and gating means responsive to said first control signal for gating said pulses to said first register for said duration.
 5. The system of claim 4 wherein said input signal comprises a plurality of discrete segments separated by time intervals, said first means determines said fundamental frequency of each of said segments, and said second means further includes; a detector responsive to said first means for detecting said fundamental frequency of each of said segments and generating a trigger output in response thereto; and means for connecting said trigger output to said generator for causing said generator to produce one of each of said first and second control pulses for each of said segments, whereby said count accumulated in said first register at a particular time is related to said fundamental frequency of one of said segments comprising said input at said particular time.
 6. The system of claim 4 wherein said input signal comprises a continuous frequency-varying wave, said first means determines said fundamental frequency for each cycle of said wave, and said second means includes: a divider responsive to said first means for generating a trigger output for every nth cycle of said wave; and means for connecting said trigger output to said generator for causing said generator to produce one of each of said First and second control pulses at ever nth one of said cycles, said duration of said first control pulse being proportional to the period of said nth cycle, so that said count accumulated in said first register is updated every nth cycle and thereby tracks the frequency of said wave, where n is any positive integer.
 7. The system of claim 6 wherein n equals four.
 8. The system of claim 3 wherein said output means includes: a second register having an initial count therein; means for changing said initial count by an amount equal to said accumulated count in said first register in a repetitive sequence; means for cycling said second register at a rate proportional to the frequency of said frequency source to cause returns of said second register to said initial count; and means for detecting said returns to said initial count and producing an output signal in response thereto whereby said output signal is repeatedly produced and has a frequency related to said fundamental frequency of said input signal.
 9. The system of claim 8 wherein said initial count equals zero, said accumulated count is added to said second register and said cycling means causes said second register to count down from said accumulated count to zero.
 10. The system of claim 8 wherein said changing means includes: a third register for receiving and storing said accumulated count from said first register; a first gate responsive to said detecting means for transferring said accumulated count from said third register to said second register upon each of said returns to said initial count; and a second gate responsive to said detecting means for transferring said accumulated count from said first register to said third register whenever a new one of said counts is accumulated in said first register whereby said third register always contains a count related to said fundamental frequency of said input signal.
 11. The system of claim 8 including: a divider between said frequency source and said first register for dividing the frequency of said pulses from said frequency source by a factor of m, where m is any positive integer; and said cycling means includes means for connecting said frequency source to said second register for causing said second register to cycle at a rate m times the rate at which said first register accumulates said count whereby said output signal has a frequency m times said frequency of said input signal.
 12. The system of claim 11 wherein m equals
 8. 13. The system of claim 8 further including division circuits for dividing said frequency of said output signal by a plurality of preselected numbers so that a plurality of outputs having frequencies related to said fundamental frequency of said input signal by any desired ratio can be obtained.
 14. The system of claim 13 further including pulse shaping circuits for shaping said plurality of outputs and means for amplifying said outputs whereby a variety of voicings having frequencies related to said frequency of said input signal can be obtained.
 15. The system of claim 3 including: a plurality of decoders each of which is responsive to the accumulation of a respective allowable count in said first register; and means responsive to said decoders in the absence of one of said respective counts for extending said period of time during which said pulses are provided to said first register until one of said respective allowable counts is accumulated in said first register, whereby said accumulated count is restricted to one of said respective allowable counts.
 16. The system of claim 15 including a subtractor between said frequency source and said first register for subtracting the first x of said pulses provided to said first register, where x is any positive integer, whereby said count accumulated in said first register is rounded off to one of the two closest ones of said Respective counts.
 17. The system of claim 16 wherein x approximately equals one-half the average difference between said respective allowable counts whereby said count accumulated in said first register is normally rounded off to the nearer one of said two closest ones of said respective counts.
 18. The system of claim 16 wherein x equals
 4. 19. The system of claim 1 including buffer and amplifier circuits for isolating and amplifying said input signal, respectively, applied to said first means.
 20. The system of claim 19 wherein said buffer circuit provides a gain of approximately one and said amplifying circuit provides a gain of approximately
 50. 21. The system of claim 1 wherein said output means comprises; a counting means having an initial count therein; means for changing said initial count by an amount proportional to said signal stored in said second means in a repetitive sequence; means for repeatedly cycling said counting means at a preselected rate to cause returns thereof to said initial count; and means for detecting said returns to said initial count and producing output signals in response thereto, said output signals having frequencies related to said fundamental frequency of said input signal.
 22. The system of claim 21 wherein said changing means includes: a storing means responsive to said signal in said second means for accumulating a count therein proportional to said signal; first gating means responsive to said detecting means for transferring said count in said storing means to said counting means each time said counting means returns to said initial count; and means responsive to the storing of a new one of said signals in said second means for updating said count accumulated in said storing means.
 23. The system of claim 22 further including division circuits for dividing said frequencies of said outputs by a plurality of preselected numbers so that a plurality of outputs having frequencies related to said fundamental frequency of said input signal by any desired ratios can be obtained.
 24. The system of claim 23 further including pulse shaping circuits for shaping said plurality of outputs and amplifying means for amplifying said plurality of outputs whereby a variety of voicings having frequencies related to said fundamental frequency of said input signal can be obtained.
 25. The system of claim 1 wherein said second means includes a first register for accumulating a pulse count therein, and a frequency source responsive to said frequency extractor for providing pulses to said first register for a period of time proportional to said fundamental frequency so that said count accumulated by said first register is proportional to said fundamental frequency; and said output means includes a second register having an initial count therein, means for changing said initial count by an amount equal to said accumulated count in said first register in a repetitive sequence, means for repetitively cycling said second register at a rate proportional to the frequency of said frequency source to cause returns thereof to said initial count, means for detecting said returns and producing output signals in response thereto, said output signals having frequencies related to said fundamental frequency and being produced in a repetitive sequence.
 26. The system of claim 25 wherein said second means further includes a generator responsive to said extractor for generating first and second control pulses, said second control pulse being utilized to initialize said first register, said first control pulse having a duration equal to said fundamental frequency, and a gate responsive to said first control pulse to transfer said pulses to said first register.
 27. The system of claim 26 including a divider for dividing the frequency of said pulses transferred to said first register by a factor of m and wherein said cycling means includes means connecting said pulses to said second regiSter to cause said second register to count at a rate m times said first register, whereby said detecting means produces an output signal having a frequency m times said fundamental frequency where m is any positive integer.
 28. The system of claim 27 wherein said changing means includes a third register for receiving and storing said accumulated count, a first gate responsive to said detecting means for transferring said accumulated count from said third register to said second register upon each of said returns of said second register to said initial count; and a second gate responsive to said detecting means and said generator means for transferring said accumulated count from said first register to said third register after the termination of each of said control pulses and during a time when said first gate is inactive.
 29. The system of claim 28 including division circuits for dividing the frequency of said output signal by a plurality of factors so that outputs having frequencies related to said fundamental frequency by any desired ratios can be obtained.
 30. The system of claim 29 wherein said plurality of factors includes the integers 1, 2, 4, 6, 8, 16, and
 32. 31. The system of claim 30 including: a plurality of decoders each of which is responsive to the accumulation of a respective allowable count in said first register; and means responsive to said decoders in the absence of one of said respective allowable counts for extending said period of time during which said pulses are provided to said first register until one of said respective counts is accumulated in said first register, whereby said accumulated count is restricted to one of said respective allowable counts.
 32. The system of claim 31 including a subtractor for subtracting the first x of said pulses transmitted by said divider towards said first register where x is any positive integer, whereby said count accumulated in said first register is rounded off to one of the two closest ones of said respective allowable counts.
 33. The system of claim 32 including means for isolating and amplifying said input signal presented to said frequency extractor.
 34. The system of claim 33 wherein said input signal comprises a continuous waveform, and including means responsive to said frequency extractor for causing said generator to produce one of each of said first and second control pulses on every nth cycle of said continuous waveform where n is any positive integer, whereby said output signal tracks said fundamental frequency of said waveform.
 35. The system of claim 25 including a second frequency source connected to said second register to cause said second register to count at a rate of m times said first register, where m is the ratio of the frequency of said second frequency source to the frequency of said frequency source, whereby said output signal produced by said detector has a frequency m times said fundamental frequency.
 36. Apparatus for generating an output signal having a frequency which is proportional to the fundamental frequency of an input signal having a frequency varying waveform comprising, in combination: a frequency extractor for extracting said fundamental frequency for each cycle of said waveform; a division circuit responsive to said extractor for producing a trigger pulse on every nth cycle of said waveform, where n is any integer; a first counting register adapted for accumulating a pulse count therein; a frequency source for providing pulses to said first register; a generator responsive to said trigger pulse for generating a second control signal for initializing said first register and a first control signal having a duration proportional to said fundamental frequency of said nth cycle; a gate responsive to said first control signal for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency of said nth cycle; a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control signals, whereby said accumulated count is updated every nth cycle; a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output at a frequency proportional to said accumulated count; and means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count to said second register, whereby said output signal has a frequency which tracks said fundamental frequency of said waveform.
 37. The system of claim 15 wherein said plurality of decoders comprises twelve decoders and said respective allowable counts have specified ratios with respect to each other.
 38. The system of claim 33 wherein said input signal comprises a plurality of discrete segments separated by time intervals and including means responsive to said frequency extractor for causing said generator to produce one of each of said first and second control pulses for each of said discrete segments, whereby the frequency of said output signal is proportional to said fundamental frequency of said discrete segments.
 39. Apparatus for generating an output signal having a frequency proportional to the fundamental frequency of a discrete segment of an input signal including a plurality of discrete segments separated by time intervals, and sustaining said output signal until a subsequent one of said discrete segments is received by said apparatus comprising, in combination; a frequency extractor for extracting said fundamental frequency of said discrete segment; a first counting register adapted for accumulating a pulse count therein; a frequency source for providing pulses to said first register; a generator responsive to said frequency extractor upon the receipt of each of said discrete segments for generating a second control pulse for initializing said first register and a first control pulse having a duration proportional to said fundamental frequency; a first gate responsive to said first control pulse for transferring said pulses to said first register to accumulate a count therein proportional to said fundamental frequency; a storage register adapted for receiving and storing said accumulated count after the termination of each of said first control pulses, whereby said accumulated count in said storage register is updated for each of said discrete segments; a second counting register having an initial count therein adapted for receiving said accumulated count from said storage register to change said initial count thereby, said second register being responsive to said frequency source to count back to said initial count and produce an output having a frequency proportional to said accumulated count and thereby to said fundamental frequency; and means responsive to a return of said second register to said initial count to cause a transfer of said accumulated count from said storage register to said second register, whereby said output signal associated with a particular one of said discrete segments is repeatedly produced until a subsequent one of said discrete sergments is received.
 40. Apparatus in accordance with claim 39 including division circuits for dividing the frequency of said output signal by a plurality of factors, whereby signals having frequencies related to said fundamental frequency by any desired ratios can be obtained. 